Summaries - Research
Back Gusty Oriole - Configurable Fault-Tolerant Architectures
|Division||Graduate School of Engineering & Applied Science|
|Department||Electrical & Computer Engineering|
Loomis, Jr., Herschel H.
Ross, Alan A.
|Sponsor||Secretary of the Air Force/FMBIB (Air Force)|
During 2011, we will continue our development efforts on building Single Event Upset (SEU) tolerant techniques for applying Field Programmable Gate Array (FPGA) technology to space-borne computing. In particular, we wish to investigate the ability of the newly discovered Reduced Precision Redundancy (RPR) technique to detect and acceptably correct SEUs in data and configuration memories in arithmetic processes in Software Defined Radios (SDRs) and other suitable algorithms on space-borne FPGAs and dedicated processors.
In this proposed research, we will test and evaluate the RPR algorithms developed by us and our students for the detection and correction of data and configuration errors using the CFTP test computers developed during our previous research. Triple Modular Redundancy will be used where necessary for non-arithmetic algorithms such as state-machine controllers.
|Publications||Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal|
|Data||Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal|