Fiscal Year	2018
Division	Graduate School of Engineering & Applied Science
Department	Electrical & Computer Engineering
Investigator(s)	Newman, James H.
Sponsor	Department of Defense Space (DoD)
Summary	During this period of performance, we will continue our development efforts on building Single Event Upset (SEU) tolerant techniques for applying Field Programmable Gate Array (FPGA) technology to space-borne computing. In particular, we plan to apply our experience in the design of fault-tolerant processors to the final design of CFTP-NPSat, the improved version of CFTP that will fly on NPSat in 2017, and after launch we will operate the experiment and analyze results.
Keywords	FPGA Fault Tolerant Reconfigurable Architectures Space
Publications	Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal
Data	Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal