Fiscal Year	2010
Division	Graduate School of Operational & Information Sciences
Department	Computer Science
Investigator(s)	Huffmire, Theodore D. Irvine, Cynthia E.
Sponsor	National Science Foundation (NSF)
Summary	In this proposal we describe the core technical method by which hardware can be augmented for security (3-D integration), and we argue that this could require very minimal changes to the host layer (with early estimates pointing to increases in areas significantly below even 1%). We plan to explore many different ways in which this new found hardware malleability could be applied, from strong isolation of cores to auditing and object reuse, but as a preliminary study we describe an initial architecture and performance analysis of a 3-D layer to eliminate cache-based side channels by re-routing signals from the host computation layer through a specialized cache manager in the control plane.
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Publications	Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal
Data	Publications, theses (not shown) and data repositories will be added to the portal record when information is available in FAIRS and brought back to the portal